1. Field of the Invention
The present invention relates generally to a method for fabricating semiconductor devices. More specifically, the present invention relates to a method for making recessed-gate Metal-Oxide-Semiconductor (MOS) transistor device of a trench type Dynamic Random Access Memory (DRAM).
2. Description of the Prior Art
Integrated circuit devices are continually being made smaller in order to increase speed, make the device more portable and to reduce the cost of manufacturing the device. However, certain designs have a minimum feature size, which cannot be reduced without compromising the integrity of electrical isolation between devices and consistent operation of the device. For example, dynamic random access memory devices (DRAMs), which use vertical metal oxide semiconductor field effect transistors (MOSFETs) with deep trench (DT) storage capacitors, have a minimum features size of approximately 70 nm˜0.15 μm. Below that size, the internal electric fields exceed the upper limit for storage node leakage, which decreases retention time below an acceptable level. Therefore, there is a need for different methods and/or different structures to further reduce the size of integrated circuit devices.
With the continued reduction in device size, sub-micron scale MOS transistors have to overcome many technical challenges. As the MOS transistors become narrower, that is, their channel length decreases, problems such as junction leakage, source/drain breakdown voltage, and data retention time become more pronounced.
One solution to decrease the physical dimension of ULSI circuits is to form recessed-gate or “trench-type” transistors, which have a gate electrode buried in a groove formed in a semiconductor substrate. This type of transistor reduces short channel effects by effectively lengthening the effective channel length by having the gate extend into the semiconductor substrate.
The recess-gate MOS transistor has a gate insulation layer formed on sidewalls and bottom surface of a recess etched into a substrate, a conductive filling the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate.
However, the aforesaid recessed-gate technology has some shortcomings. For example, the recess for accommodating the recessed gate of the MOS transistor is etched into a semiconductor wafer by using conventional dry etching methods. It is difficult to control the dry etching and form recesses having the same depth across the wafer. A threshold voltage control problem arises because of recess depth variation.
Furthermore, the aforesaid recessed-gate technology requires at least two steps of polysilicon deposition and a lithography process. The first deposited polysilicon layer is used to form a gate structure of the support circuit area, and a lithography process is required to remove the first deposited polysilicon layer and a silicon oxide layer deposited on the memory array area. Then, a second deposited polysilicon layer is used to form a gate structure of the memory array area. However, when over etching happens in removing the silicon oxide layer and bias or misalignment happens in defining the gate structure, the second deposited polysilicon layer may short with the substrate.
Additionally, the aforesaid recessed-gate technology requires another mask to define the recessed-gate since the large misalignment will reduce the landing area of the source and drain, and increase the bit line contact resistance.